Magnetoelectronic devices, spin electronic devices, and spintronic devices are synonymous terms for devices that make use of effects predominantly caused by electron spin. Magnetoelectronics are used in numerous information devices to provide non-volatile, reliable, radiation resistant, and high-density data storage and retrieval. The numerous magnetoelectronics information devices include, but are not limited to, Magnetoresistive Random Access Memory (MRAM), magnetic sensors, and read/write heads for disk drives.
Typically an MRAM includes an array of magnetoresistive memory elements. Each magnetoresistive memory element typically has a structure that includes multiple magnetic layers separated by various non-magnetic layers, such as a magnetic tunnel junction (MTJ), and exhibits an electrical resistance that depends on the magnetic state of the device. Information is stored as directions of magnetization vectors in the magnetic layers. Magnetization vectors in one magnetic layer are magnetically fixed or pinned, while the magnetization direction of another magnetic layer may be free to switch between the same and opposite directions that are called “parallel” and “antiparallel” states, respectively. Corresponding to the parallel and antiparallel magnetic states, the magnetic memory element has low (logic “0” state) and high (logic “1” state) electrical resistance states, respectively. Accordingly, a detection of the resistance allows a magnetoresistive memory element, such as an MTJ device, to provide information stored in the magnetic memory element. A high magnetoresistance (MR) value, which is the ratio of the resistance difference of the two states to the low resistance state, is desirable for increasing sensing signal and fast read operation.
There are two completely different methods used to program the free layer: field switching and spin-torque switching. In field-switched MRAM, current carrying lines adjacent to the MTJ bit are used to generate magnetic fields that act on the free layer. In spin-torque MRAM, switching is accomplished with a current pulse through the MTJ itself. The angular momentum carried by the spin-polarized tunneling current causes reversal of the free layer, with the final state (parallel or antiparallel) determined by the polarity of the current pulse. A reset current pulse will cause the final state to be parallel or logic “0”. A set current pulse, in the opposite polarity of reset current pulse, will cause the final state to be antiparallel or logic “1”. Spin-torque transfer is known to occur in MTJ devices and giant magnetoresistance devices that are patterned or otherwise arranged so that the current flows substantially perpendicular to the interfaces, and in simple wire-like structures when the current flows substantially perpendicular to a domain wall. Any such structure that exhibits magnetoresistance has the potential to be a spin-torque magnetoresistive memory element.
Spin-torque MRAM (ST-MRAM), also known as spin-transfer torque RAM (STT-RAM), is an emerging memory technology with the potential for non-volatility with unlimited endurance and fast write speeds at much higher density than field-switched MRAM. Since ST-MRAM switching current requirements reduce with decreasing MTJ dimensions, ST-MRAM has the potential to scale nicely at even the most advanced technology nodes. However, increasing variability in MTJ resistance and sustaining relatively high switching currents through bit cell select devices in both current directions can limit the scalability of ST-MRAM. The write current is typically higher in one direction compared to the other, so the select device must be capable of passing the larger of the two currents. In addition, ST-MRAM switching current requirements increase as the write current pulse duration is reduced. Because of this, the smallest ST-MRAM bitcell approach may require relatively long switching times.
The conventional scheme for programming spin-torque MRAM is to apply a single current or voltage pulse to the memory cells to reverse the direction of their storage layer. The duration of the pulse is set by design requirements such as memory interface specifications. Generally, the write operation has to be completed in less than 50 ns. The write voltage amplitude is set to meet the memory write error rate (WER) and lifetime requirements. It has to be greater than a certain value Vw to assure that all bits are programmed reliably, with a write error rate below a defined value WER0. For megabit memories, WER0 is typically less than 10−8. The write voltage amplitude also has to be low enough to assure long-term device integrity. For magnetic tunnel junctions, elevated write voltage reduces the memory lifetime because of dielectric breakdown. In some cases, it is not possible to find a write voltage that meets the desired write error rate WER0 and the required lifetime. Known solutions to improve the write error rate are adding one or several layers of error correction or using multiple write pulses.
An ST-MRAM array includes a plurality of core strips, with each core strip including a bit cell array comprising a plurality of columns of bit cells (a magnetic tunnel junction and a word line select transistor). In a column of ST-MRAM bit cells, only one row is selected for reading or writing with a positive voltage at the gate (control electrode) of the word line select transistor.
In a column of bit cells, a first end of the magnetic tunnel junctions is connected to a first common line referred to as bit line. The second end of the magnetic tunnel junctions connects to the first current carrying electrode of their respective word line select transistor. The second current carrying electrodes of the word line select transistors are connected to a second common line referred to as source line. Due to a large number, for example 512 or 1024, of bit cells in a column, bit and source lines are long metal routes that can have significant resistance. When writing a bit far away from either the top or bottom end of a column using a write driver, current through the bit and source lines causes voltage drop due to line resistance reducing the applied voltage across the magnetic tunnel junction.
It is desirable to reduce effective resistance of all the components, for example metal resistance and word line select device resistance, in the path during reading from or writing to a selected bit cell by applying different voltages at its bit line and source line. In order to reduce the resistance from the word line select device, the gate (control electrode) can be charge pumped to a higher voltage than the supply voltage. However, the pumped word line gate voltage raises the possibility of time dependent dielectric breakdown (TDDB). One known circuit (see U.S. Pat. No. 7,190,612) discloses a NAND gate output going to an inverter and controls two switches, for example, one switch connecting the bit line or source line to a first reference voltage and a second switch connecting the bit line or source line to a second reference voltage. However, this known patent teaches the voltage applications being controlled by the same timing signal. Pumped word line voltages may cause reliability problems in such an implementation.
Another circuit (see U.S. Patent Publication Number 2010/0110775A1) describes pumped word line voltages, and separate switches for read, write with set current pulse, and write with reset current pulse. However, there is no disclosure of timing control for write and read switches, and the pumped word line voltages can cause reliability problems.
Accordingly, circuitry for sense amplifiers, write drivers, and column selection is needed that provides a higher write voltage across the magnetic tunnel junction during write and higher effective MR during read, while avoiding time dependent dielectric breakdown (TDDB) stress of the word line select devices in the selected row. Furthermore, other desirable features and characteristics of the exemplary embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.